Support the development of our ICs with reliable and high quality layout and floorplanning
Do you want to be part of the IoT revolution? e-peas is a startup company founded in 2014 on the conviction that the trillions of connected nodes of the IoT that will be deployed in the next few years will require disruptive solutions to extend batteries life-time. At e-peas, we believe that new applications will ultimately be made possible by the combination of two approaches:
- The increase of the harvested energy provided to the system
- The reduction of the energy consumption of all power consuming integrated circuits of the system
Relying on 15 years of research and its patented disruptive technologies, e-peas offers a portfolio of integrated circuits including photovoltaic and thermoelectric harvester interfaces, microcontrollers and sensor solutions.
What will be your job? In order to strengthen our development team, we are looking for a designer to perform the layout of our ICs. You will deliver the layout of the analog sub-circuits such as voltage references, oscillators, DC/DC converters, etc. You will also be in charge of the system top-level assembly and therefore be responsible for the floor-planning and verification of complex circuits. You will ensure that the design meets the manufacturer rules with a special attention to design for manufacturing (DFM) requirements. You will closely work with the development teams and interact with the analog designers on specific layout topics such as device matching or noise coupling reduction.
Your daily tasks include:
- Layout of analog sub-circuits
- Interactions with the development team on layout specifications and requirements
- Optimization of layouts such as device matching and parasitic reduction
- Top level assembly
- Interpretation and solving of LVS checks
- Solving DRC, antenna and DFM checks
What is your experience?
- BS/MS in Electronic Engineering within the field of microelectronic design or relevant proven experience
- 5 years or more experience in integrated circuit layout in submicron CMOS technology
- Expertise in analog layout care-abouts like parasitic reduction, device matching, etc.
- Good knowledge of Cadence Virtuoso tool and Mentor Calibre tool
- Fluent in French (a plus) and English
- Besides being a smart engineer, you are:
- Rigorous and quality-minded
- Autonomous, while being also a great team player
What will e-peas offer you? Beyond an attractive compensation and benefits package, you will get the unique chance to join the adventure of building up a high-potential company at the cutting-edge of technology with a young and motivated team. In addition you will have the opportunity to develop your career and experience as e-peas grows-up.
Up to the challenge? If you feel interested, send us your CV and motivation letter at: firstname.lastname@example.org